High-performance parallel computing for next-generation holographic imaging

次世代ホログラフィックイメージング向けの高性能並列演算

[Abstract] Holography is a leading method of recording and reproducing 3D images. The increasingly widespread availability of computers has encouraged the development of holographic 3D screens (electroholography). Although electroholography was first proposed a half-century ago, it has not been used in practical applications. A fundamental problem is the enormous volume of data that a hologram requires. Even modern computational power is inadequate to process this volume of data in real time. The area from which the reconstructed image can be viewed is determined by the way in which the light diffracted by the hologram is spread, and this in turn depends on the pixel pitch of the hologram. A smaller pitch creates a wider viewing angle. At a pixel pitch of 1 μm, the viewing angle extends to 30°, thus making it practical for everyday applications. The pixel pitch of a typical current liquid crystal display is approaching this limit. However, a high-definition display device requires a large number of pixels, thus making processing challenging. At a 1 μm pixel pitch, even a display device that is 1 cm × 1 cm in size would require 100 million (108) pixels. Our group has been pursuing a five-year project with the goal of realising an arithmetic circuit that is able to drive a video-rate 1 cm × 1 cm computer-generated hologram of 108 pixels at a pixel pitch of 1 μm. In the course of this research, we have developed a special-purpose holography computing board by using eight large-scale field-programmable gate arrays (FPGAs). This computing board is far beyond the scope of current commercial offerings. We have also succeeded in achieving a parallel operation of 4,480 hologram calculation circuits on a single board. By clustering eight of these boards, we succeeded in increasing the number of parallel calculations to 35,840, thus allowing computations to be performed 1,000 times faster than those of a personal computer. By using a 3D image comprising 7,877 points, we succeeded in updating 108-pixel holograms at a video rate, thus allowing 3D movies to be projected. We further demonstrated that the system speed scales up in a linear manner as the number of parallel circuits is increased. The system operates at 0.25 GHz with an effective speed equivalent to 0.5 Pflops (1015 floating-point operations per second), matching that of a high-performance computer. These results suggest that a holographic 3D image system can be constructed using currently available technology. In a further step, we will upgrade the system to a large-scale integration (LSI) circuit that is 1 cm × 1 cm in size by using existing technology. Coupling this LSI to a 108-pixel display would create a chip dedicated to holography. Given that the computation of a hologram treats each pixel independently, a suitable arrangement of these dedicated chips could create a 3D video system of arbitrary size and shape (hemispherical, spherical, cylindrical, etc.). As one of immediate goals, we can create a wide 3D projection space by incorporating our dedicated chip into a head-mounted display.

https://opac.ll.chiba-u.jp/da/curator/105754/

https://opac.ll.chiba-u.jp/da/curator/105754/HORN8_Nature_Electronics_2017_12_30_v1.pdf

Preprint

2017-12-30

https://doi.org/10.1038/s41928-018-0057-5

eng

https://doi.org/10.1038/s41928-018-0057-5

author

IGPR201811: A big step toward the practical application of 3D holography with high- performance computers

Final version appeared in Nature Electronics, Vol. 1, pp. 254–259 (2018). doi: 10.1038/s41928-018-0057-5